AVR / FPGA 應用整合邏輯 2
實驗2是延續實驗1的,不同的是, 在實驗2, 是將AVR的PORT A經由FPGA, 轉換輸出至CMOS模組上的七段顯示器
Source
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VHDL : gcpudig.vhd |
Verilog : gcpudig.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY gcpudig IS PORT ( mclk : IN STD_LOGIC; pa : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dd : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); ds : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END gcpudig;
ARCHITECTURE a1 OF gcpudig IS SIGNAL pcnt : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
-- Counter for Multiplexing PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN pcnt<=pcnt+1; END IF; END PROCESS;
-- Digits Multiplexer PROCESS(pcnt,pa) VARIABLE dmux : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF pcnt(7)='1' THEN dmux:=pa(7 DOWNTO 4); ds<="01"; ELSE dmux:=pa(3 DOWNTO 0); ds<="10"; END IF;
-- Decoder of 7-Segment Display CASE dmux IS WHEN "0000" => dd<="1000000"; WHEN "0001" => dd<="1111001"; WHEN "0010" => dd<="0100100"; WHEN "0011" => dd<="0110000"; WHEN "0100" => dd<="0011001"; WHEN "0101" => dd<="0010010"; WHEN "0110" => dd<="0000010"; WHEN "0111" => dd<="1111000"; WHEN "1000" => dd<="0000000"; WHEN "1001" => dd<="0010000"; WHEN "1010" => dd<="0001000"; WHEN "1011" => dd<="0000011"; WHEN "1100" => dd<="1000110"; WHEN "1101" => dd<="0100001"; WHEN "1110" => dd<="0000110"; WHEN "1111" => dd<="0001110"; WHEN OTHERS => dd<="1111111"; END CASE; END PROCESS;
END a1;
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module gcpudig ( mclk,pa,dd,ds ); input mclk; input[7:0] pa; output[6:0] dd; output[1:0] ds;
reg[1:0] ds; reg[3:0] dmux; reg[6:0] dd; reg[7:0] pcnt;
// Counter for Multiplexing always @(posedge mclk) pcnt<=pcnt+1;
// Digits Multiplexer always @(pcnt or pa) begin if(pcnt[7]) begin dmux=pa[7:4]; ds=2'b01; end else begin dmux=pa[3:0]; ds=2'b10; end
// Decoder of 7-Segment Display case(dmux) 4'h0 : dd=~(7'b0111111); 4'h1 : dd=~(7'b0000110); 4'h2 : dd=~(7'b1011011); 4'h3 : dd=~(7'b1001111); 4'h4 : dd=~(7'b1100110); 4'h5 : dd=~(7'b1101101); 4'h6 : dd=~(7'b1111101); 4'h7 : dd=~(7'b0000111); 4'h8 : dd=~(7'b1111111); 4'h9 : dd=~(7'b1101111); 4'ha : dd=~(7'b1110111); 4'hb : dd=~(7'b1111100); 4'hc : dd=~(7'b0111001); 4'hd : dd=~(7'b1011110); 4'he : dd=~(7'b1111001); 4'hf : dd=~(7'b1110001); endcase end
endmodule
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