A1K & XC2S 應用整合邏輯 .6

Numeric Control Oscillator實驗

這是一個數值控制振盪器(NCO), 用數值改變所產生正弦波(或其他波形)的頻率:設定CMOS模組的DIP SW,作為數值輸入,輸出分別至ADDA模組(接示波器), --NCO有連續的相位,可用在通訊,如FSK

此一範例包含兩組不同頻率的NCO; NCO是由一個相位的累加器(fcnta,fcntb),及一個將相位對應至輸出的函數(fsina,fsinb); DAC的CH0輸出第一個NCO(fcnta)的相位; CH1輸出第一個NCO的函數fsina; CH2輸出第二個NCO的函數fsinb; CH3輸出這兩個NCO的函數的和fsum=fsina+fsinb; fsina,fsinb頻率接近但不相同時, fsum可看出有拍(beat)的封包

Source

1. 建立FPGA的Project : vmsdac

Verilog : vmsdac.v

module vmsdac

(

mclk,nrst,

frq,

scko,sdo,scso,sldo,sclo

);

input mclk,nrst;

input[11:0] frq;

output scko,sdo,scso,sldo,sclo;

reg nrstn,nrstp,pmov,pcov;

reg[1:0] ais;

reg[6:0] pcnt;

reg[7:0] di;

wire[7:0] fsina,fsinb;

wire[8:0] fsum;

reg[11:0] frqs;

reg[15:0] fcnta,fcntb;

wire ldi;

assign sclo=1'b1;

msdac msdac(mclk,nrstp,2'b11,ais,di,ldi,scko,sdo,scso,sldo,);

// synchronization

always @(posedge mclk)

nrstn<=nrst;

always @(posedge mclk)

nrstp<=nrstn;

always @(posedge mclk)

frqs<=frq;

always @(posedge mclk or negedge nrstp)

begin

if(~nrstp)

begin

pcnt<=0; pmov<=0; pcov<=0; ais<=0;

end

else

begin

pcnt<=pcnt+1;

pmov<=(pcnt[4:0]==5'h1f);

pcov<=(pcnt==7'h7f);

ais<=pcnt[6:5];

end

always @(posedge mclk or negedge nrstp)

begin

if(~nrstp)

begin

fcnta<=0; fcntb<=0;

end

else

begin

if(pcov) begin

fcnta<=fcnta+frqs;

fcntb<=fcntb+{frqs[11:5],5'b00};

end

assign ldi=pmov;

always @(ais or fcnta or fsina or fsinb or fsum)

begin

case(ais)

2'b00 : begin

di=fcnta[15:8];

end

2'b01 : begin

di=fsina;

end

2'b10 : begin

di=fsinb;

end

2'b11 : begin

di=fsum[8:1];

end

default : begin

di=0;

end

endcase

end

fsin fsa(mclk,fcnta[15:8],fsina);

fsin fsb(mclk,fcntb[15:8],fsinb);

assign fsum={1'b0,fsina}+{1'b0,fsinb};

endmodule

Verilog : msdac.v

module msdac

(

mclk,nrst,

si,ai,di,ldi,

scko,sdo,scso,sldo,

busyo

);

input mclk,nrst,ldi;

input[1:0] si,ai;

input[7:0] di;

output scko,sdo,scso,sldo,busyo;

parameter MSS_IDLE=3'b000,MSS_SHF=3'b011,MSS_LD=3'b101;

reg[11:0] sreg,nsreg;

reg[4:0] scnt,nscnt;

reg[2:0] mss,nmss;

reg scov,scko,sdo,scso,sldo,busyo;

always @(posedge mclk)

begin

if(~nrst)

begin mss<=0; sreg<=0; scnt<=0; end

else

begin mss<=nmss; sreg<=nsreg; scnt<=nscnt; end

end

always @(mss or sreg or scnt or ldi or si or ai or di or scov)

begin

sdo=sreg[11];

nsreg=sreg; nmss=mss;

case(mss)

MSS_IDLE :

begin

if(ldi) nsreg={si,ai,di};

nscnt=0;

scko=1'b0; scso=1'b1; sldo=1'b1; busyo=1'b1;

if(ldi) nmss=MSS_SHF;

end

MSS_SHF :

begin

if(scnt[0]) nsreg={sreg[10:0],1'b0};

nscnt=scnt+1;

scko=scnt[0]; scso=1'b0; sldo=1'b1; busyo=1'b0;

if(scov) nmss=MSS_LD;

end

MSS_LD :

begin

nscnt=scnt+1;

scko=1'b0; scso=1'b1; sldo=1'b0; busyo=1'b1;

nmss=MSS_IDLE;

end

default :

begin

nscnt=0; nsreg=sreg;

scko=1'b0; scso=1'b1; sldo=1'b1; busyo=1'b1;

nmss=MSS_IDLE;

end

endcase

end

always @(posedge mclk)

begin

scov<=(scnt==22);

end

endmodule

Verilog : fsin.v

module fsin

(

mclk,

phi,

sino

);

input mclk;

input[7:0] phi;

output[7:0] sino;

reg[7:0] sino;

always @(posedge mclk)

begin

case(phi)

0 : sino<=128;

1 : sino<=131;

2 : sino<=134;

3 : sino<=137;

4 : sino<=140;

5 : sino<=144;

6 : sino<=147;

7 : sino<=150;

8 : sino<=153;

9 : sino<=156;

10 : sino<=159;

11 : sino<=162;

12 : sino<=165;

13 : sino<=168;

14 : sino<=171;

15 : sino<=174;

16 : sino<=177;

17 : sino<=179;

18 : sino<=182;

19 : sino<=185;

20 : sino<=188;

21 : sino<=191;

22 : sino<=193;

23 : sino<=196;

24 : sino<=199;

25 : sino<=201;

26 : sino<=204;

27 : sino<=206;

28 : sino<=209;

29 : sino<=211;

30 : sino<=213;

31 : sino<=216;

32 : sino<=218;

33 : sino<=220;

34 : sino<=222;

35 : sino<=224;

36 : sino<=226;

37 : sino<=228;

38 : sino<=230;

39 : sino<=232;

40 : sino<=234;

41 : sino<=235;

42 : sino<=237;

43 : sino<=239;

44 : sino<=240;

45 : sino<=241;

46 : sino<=243;

47 : sino<=244;

48 : sino<=245;

49 : sino<=246;

50 : sino<=248;

51 : sino<=249;

52 : sino<=250;

53 : sino<=250;

54 : sino<=251;

55 : sino<=252;

56 : sino<=253;

57 : sino<=253;

58 : sino<=254;

59 : sino<=254;

60 : sino<=254;

61 : sino<=255;

62 : sino<=255;

63 : sino<=255;

64 : sino<=255;

65 : sino<=255;

66 : sino<=255;

67 : sino<=255;

68 : sino<=254;

69 : sino<=254;

70 : sino<=254;

71 : sino<=253;

72 : sino<=253;

73 : sino<=252;

74 : sino<=251;

75 : sino<=250;

76 : sino<=250;

77 : sino<=249;

78 : sino<=248;

79 : sino<=246;

80 : sino<=245;

81 : sino<=244;

82 : sino<=243;

83 : sino<=241;

84 : sino<=240;

85 : sino<=239;

86 : sino<=237;

87 : sino<=235;

88 : sino<=234;

89 : sino<=232;

90 : sino<=230;

91 : sino<=228;

92 : sino<=226;

93 : sino<=224;

94 : sino<=222;

95 : sino<=220;

96 : sino<=218;

97 : sino<=216;

98 : sino<=213;

99 : sino<=211;

100 : sino<=209;

101 : sino<=206;

102 : sino<=204;

103 : sino<=201;

104 : sino<=199;

105 : sino<=196;

106 : sino<=193;

107 : sino<=191;

108 : sino<=188;

109 : sino<=185;

110 : sino<=182;

111 : sino<=179;

112 : sino<=177;

113 : sino<=174;

114 : sino<=171;

115 : sino<=168;

116 : sino<=165;

117 : sino<=162;

118 : sino<=159;

119 : sino<=156;

120 : sino<=153;

121 : sino<=150;

122 : sino<=147;

123 : sino<=144;

124 : sino<=140;

125 : sino<=137;

126 : sino<=134;

127 : sino<=131;

128 : sino<=128;

129 : sino<=125;

130 : sino<=122;

131 : sino<=119;

132 : sino<=116;

133 : sino<=112;

134 : sino<=109;

135 : sino<=106;

136 : sino<=103;

137 : sino<=100;

138 : sino<=97;

139 : sino<=94;

140 : sino<=91;

141 : sino<=88;

142 : sino<=85;

143 : sino<=82;

144 : sino<=79;

145 : sino<=77;

146 : sino<=74;

147 : sino<=71;

148 : sino<=68;

149 : sino<=65;

150 : sino<=63;

151 : sino<=60;

152 : sino<=57;

153 : sino<=55;

154 : sino<=52;

155 : sino<=50;

156 : sino<=47;

157 : sino<=45;

158 : sino<=43;

159 : sino<=40;

160 : sino<=38;

161 : sino<=36;

162 : sino<=34;

163 : sino<=32;

164 : sino<=30;

165 : sino<=28;

166 : sino<=26;

167 : sino<=24;

168 : sino<=22;

169 : sino<=21;

170 : sino<=19;

171 : sino<=17;

172 : sino<=16;

173 : sino<=15;

174 : sino<=13;

175 : sino<=12;

176 : sino<=11;

177 : sino<=10;

178 : sino<=8;

179 : sino<=7;

180 : sino<=6;

181 : sino<=6;

182 : sino<=5;

183 : sino<=4;

184 : sino<=3;

185 : sino<=3;

186 : sino<=2;

187 : sino<=2;

188 : sino<=2;

189 : sino<=1;

190 : sino<=1;

191 : sino<=1;

192 : sino<=1;

193 : sino<=1;

194 : sino<=1;

195 : sino<=1;

196 : sino<=2;

197 : sino<=2;

198 : sino<=2;

199 : sino<=3;

200 : sino<=3;

201 : sino<=4;

202 : sino<=5;

203 : sino<=6;

204 : sino<=6;

205 : sino<=7;

206 : sino<=8;

207 : sino<=10;

208 : sino<=11;

209 : sino<=12;

210 : sino<=13;

211 : sino<=15;

212 : sino<=16;

213 : sino<=17;

214 : sino<=19;

215 : sino<=21;

216 : sino<=22;

217 : sino<=24;

218 : sino<=26;

219 : sino<=28;

220 : sino<=30;

221 : sino<=32;

222 : sino<=34;

223 : sino<=36;

224 : sino<=38;

225 : sino<=40;

226 : sino<=43;

227 : sino<=45;

228 : sino<=47;

229 : sino<=50;

230 : sino<=52;

231 : sino<=55;

232 : sino<=57;

233 : sino<=60;

234 : sino<=63;

235 : sino<=65;

236 : sino<=68;

237 : sino<=71;

238 : sino<=74;

239 : sino<=77;

240 : sino<=79;

241 : sino<=82;

242 : sino<=85;

243 : sino<=88;

244 : sino<=91;

245 : sino<=94;

246 : sino<=97;

247 : sino<=100;

248 : sino<=103;

249 : sino<=106;

250 : sino<=109;

251 : sino<=112;

252 : sino<=116;

253 : sino<=119;

254 : sino<=122;

255 : sino<=125;

default : sino<=0;

endcase

end

endmodule

1. The DIP switch input freq controls the phase increasing rates of the counters fcnta and fcntb, which in turns manage the output frequencies of the sine tables sina and sinb.

2. Four signals: phase of fcnta, sina, sinb, sina+sinb, are multiplexed to the DAC control module msdac, steering the four outputs of the DAC chip respectively.

3. pcnt scales down the system clock at a factor of 128 by the signal pcov. The accumulators add the phase freq for every one pcnt cycle. In the meanwhile, the four signals are loaded into DAC chip by msdac control module sequencially at the period of pmov.

4. The phase increments of the two counters are different slightly( frqs[11:0] and (frqs[11:5],5'b0) ) for demonstrating the beat effect of the summing signal sina+sinb.

5. msdac : The data to be shifted to the DAC chip are loaded to the register sreg[11:0] when ldi(pmov) asserts. The state machine mss then shifts this register for 11 cycles, feeding the 12 bits data to the DAC chip.

6. The following figure is the block diagram of the AD7304. The AD7304 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. New serial data is clocked into the serial input register in a 12-bit data-word format in the following figure. MSB bits are loaded first.

7. Data can only be clocked in while the CS chip select pin is active low. Only the last 12-bits clocked into the serial register will be interrogated and loaded to the addressed(by A1,A0) input register, when the CS pin returns to the logic high state, extra data bits are ignored.

8. If Bit 11 (SA), Shutdown All Channels, is set to logic LOW, all DACs are placed in a power shutdown mode, all output voltages become high resistance. If Bit 10 (SI), Shutdown Decoded Channel, is set to logic LOW, only the DAC decoded by address bits A1 and A0 is placed in the shutdown mode.

9. The asynchronous input CLR pin forces all input and DAC registers to the zero-code state. The asynchronous LDAC pin can be pulsed to active low when all DAC Registers need to be updated simultaneously from their respective Input Registers. The LDAC pin places the DAC Register in a transparent mode while in the logic low state.

zeppe

ZEPPE

zeppe 發表在痞客邦留言(0) 人氣(200)

ZEPPE

FPGA / ARM / DSP / Memory / Audio / CMOS / VGA / ARM&DSP ICE

A1K & XC2S 應用整合邏輯 .6

文章分類

最新文章

文章搜尋