基本邏輯2 解碼器和編碼器
程式設計者可以練習解碼器和編碼器
程式設計者可以練習使用Case Statement
特別注意各種encoder的差異
-- decode
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VHDL : decode.vhd |
Verilog : decode.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY decode IS PORT ( a : IN STD_LOGIC_VECTOR(1 DOWNTO 0); d : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END decode; ARCHITECTURE a1 OF decode IS BEGIN
WITH a SELECT d<= "0001" WHEN "00", "0010" WHEN "01", "0100" WHEN "10", "1000" WHEN "11", "----" WHEN OTHERS; --PROCESS(a) --BEGIN --CASE(a) --WHEN "00" => d<="0001"; --WHEN "01" => d<="0010"; --WHEN "10" => d<="0100"; --WHEN "11" => d<="1000"; --WHEN OTHERS d<="----"; --END CASE; --END PROCESS; --PROCESS(a) --BEGIN --IF a="00" THEN d<="0001"; --ELSIF a="01" THEN d<="0010"; --ELSIF a="10" THEN d<="0100"; --ELSIF a="11" THEN d<="1000"; --END IF; --END PROCESS;
END a1;
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module decode ( a, d );
input[1:0] a; output[3:0] d;
reg[3:0] d;
always @(a) begin if(a==2'b00) d=4'b0001; else if(a==2'b01) d=4'b0010; else if(a==2'b10) d=4'b0100; else if(a==2'b11) d=4'b1000; end
//always @(a) //case(a) //2'b00 : d[]=4'b0001; //2'b01 : d[]=4'b0010; //2'b10 : d[]=4'b0100; //2'b11 : d[]=4'b1000; //endcase //end
endmodule
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-- encode
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VHDL : encode.vhd |
Verilog : encode.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY encode IS PORT ( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); d : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END encode;
ARCHITECTURE a1 OF encode IS BEGIN
PROCESS(a) BEGIN IF a="1000" THEN d<="11"; ELSIF a="0100" THEN d<="10"; ELSIF a="0010" THEN d<="01"; ELSIF a="0001" THEN d<="00"; ELSE d<="00"; END IF; END PROCESS;
--PROCESS(a) --BEGIN --CASE a IS --WHEN "1000" => d<="11"; --WHEN "0100" => d<="10"; --WHEN "0010" => d<="01"; --WHEN "0001" => d<="00"; --WHEN OTHERS => d<="00"; --END CASE; --END PROCESS;
END a1;
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module encode ( a,d ); input[3:0] a; output[1:0] d;
always @(a) begin if(a==4'b1000) d=2'b11; else if(a==4'b0100) d=2'b10; else if(a==4'b0010) d=2'b01; else if(a==4'b0001) d=2'b00; else d=2'b00; end
endmodule
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-- encodea
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VHDL : encodea.vhd |
Verilog : encodea.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY encodea IS PORT ( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); d : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END encodea;
ARCHITECTURE a1 OF encodea IS BEGIN
PROCESS(a) BEGIN IF a(3)='1' THEN d<="11"; ELSIF a(2)='1' THEN d<="10"; ELSIF a(1)='1' THEN d<="01"; ELSIF a(0)='1' THEN d<="00"; ELSE d<="00"; END IF; END PROCESS;
END a1;
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module encodea ( a,d ); input[3:0] a; output[1:0] d;
reg[1:0] d;
always @(a) begin if(a==4'b1xxx) d=2'b11; else if(a==4'bx1xx) d=2'b10; else if(a==4'bxx1x) d=2'b01; else if(a==4'bxxx1) d=2'b00; else d=2'b00; end
endmodule
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-- encodeb
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VHDL : encodeb.vhd |
Verilog : encodeb.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY encodeb IS PORT ( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); d : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END encodeb;
ARCHITECTURE a1 OF encodeb IS BEGIN
-- no prority, make sure at most one 1's in a[]
-- Incorrect --PROCESS(a) --BEGIN --CASE a IS --WHEN "1---" => d<="11"; --WHEN "-1--" => d<="10"; --WHEN "--1-" => d<="01"; --WHEN "---1" => d<="00"; --WHEN OTHERS => d<="00"; --END CASE; --END PROCESS; d(1)<=a(3) OR a(2); d(0)<=a(3) OR a(1);
END a1;
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module encodeb ( a, d );
input[3:0] a; output[1:0] d;
reg[1:0] d;
always @(a) begin casex(a) 4'b1xxx : d=2'b11; 4'bx1xx : d=2'b10; 4'bxx1x : d=2'b01; 4'bxxx1 : d=2'b00; default : d=2'b00; endcase end
endmodule
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