基本邏輯 .3 Multiplexer (多功器)
程式設計者可以練習和了解Multiplexer
程式設計者可以練習階層式(Hirachical)繪圖法
-- mux2
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VHDL : mux2.vhd |
Verilog : mux2.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY mux2 IS PORT ( a,b,s : IN STD_LOGIC; y : OUT STD_LOGIC ); END mux2;
ARCHITECTURE a1 OF mux2 IS BEGIN
PROCESS(a,b,s) BEGIN IF s='1' THEN y<=b; ELSE y<=a; END IF; END PROCESS;
END a1;
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module mux2 ( a,b,s, y );
input a,b,s; output y;
reg y;
always @(s or a or b) begin if(s) y=b; else y=a; end //assign y=s&b | ~s&a;
endmodule
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-- mux4
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VHDL : mux4.vhd |
Verilog : mux4.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY mux4 IS PORT ( a,b,c,d : IN STD_LOGIC; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC ); END mux4;
ARCHITECTURE a1 OF mux4 IS BEGIN
PROCESS(s,a,b,c,d) BEGIN CASE s IS WHEN "00" => y<=a; WHEN "01" => y<=b; WHEN "10" => y<=c; WHEN "11" => y<=d; WHEN OTHERS => y<='0'; END CASE; END PROCESS;
END a1;
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module mux4 ( a,b,c,d,s, y );
input a,b,c,d; input[1:0] s; output y;
reg y;
always @(s or a or b or c or d) begin case(s) 2'b00 : y=a; 2'b01 : y=b; 2'b10 : y=c; 2'b11 : y=d; endcase end
endmodule
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-- mux44
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VHDL : mux44.vhd |
Verilog : mux44.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY mux44 IS PORT ( a,b,c,d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END mux44;
ARCHITECTURE a1 OF mux44 IS BEGIN
PROCESS(s,a,b,c,d) BEGIN CASE s IS WHEN "00" => y<=a; WHEN "01" => y<=b; WHEN "10" => y<=c; WHEN "11" => y<=d; WHEN OTHERS => y<="0000"; END CASE; END PROCESS;
END a1;
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module mux44 ( a,b,c,d,s, y );
input[3:0] a,b,c,d; input[1:0] s; output[3:0] y;
reg[3:0] y;
always @(s or a or b or c or d) begin case(s) 2'b00 : y=a; 2'b01 : y=b; 2'b10 : y=c; 2'b11 : y=d; endcase end
//assign y={4{~s[1]&~s[0]}}&a | {4{~s[1]&s[0]}}&b | {4{s[1]&~s[0]}}&c | {4{s[1]&s[0]}}&d;
endmodule
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