基本邏輯4 Full Adder(全加器)
程式設計者可以練習Full Adder
這個實驗可以練習使用+運算元的Behavioral Statement
-- fadd
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VHDL : fadd.vhd |
Verilog : fadd.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY fadd IS PORT ( cin,a,b : IN STD_LOGIC; s,cout : OUT STD_LOGIC ); END fadd;
ARCHITECTURE a1 OF fadd IS BEGIN
s<=cin XOR a XOR b;
cout<=(cin AND a) OR (cin AND b) OR (a AND b);
END a1;
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module fadd ( cin,a,b, s,cout );
input cin,a,b; output s,cout;
assign s=cin^a^b; assign cout=cin&a | cin&b | a&b;
endmodule
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-- add8
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VHDL : add8.vhd |
Verilog : add8.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY add8 IS PORT ( cin : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); cout : OUT STD_LOGIC ); END add8;
ARCHITECTURE a1 OF add8 IS SIGNAL cy : STD_LOGIC_VECTOR(6 DOWNTO 0); COMPONENT fadd PORT (cin,a,b : IN STD_LOGIC; s,cout : OUT STD_LOGIC); END COMPONENT; BEGIN
u0 : fadd PORT MAP(cin,a(0),b(0),s(0),cy(0)); u1 : fadd PORT MAP(cy(0),a(1),b(1),s(1),cy(1)); u2 : fadd PORT MAP(cy(1),a(2),b(2),s(2),cy(2)); u3 : fadd PORT MAP(cy(2),a(3),b(3),s(3),cy(3)); u4 : fadd PORT MAP(cy(3),a(4),b(4),s(4),cy(4)); u5 : fadd PORT MAP(cy(4),a(5),b(5),s(5),cy(5)); u6 : fadd PORT MAP(cy(5),a(6),b(6),s(6),cy(6)); u7 : fadd PORT MAP(cy(6),a(7),b(7),s(7),cout);
END a1;
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module add8 ( cin,a,b, s,cout );
input cin; input[7:0] a,b; output cout; output[7:0] s;
wire[6:0] cy;
fadd fa0(cin,a[0],b[0],s[0],cy[0]), fa1(cy[0],a[1],b[1],s[1],cy[1]), fa2(cy[1],a[2],b[2],s[2],cy[2]), fa3(cy[2],a[3],b[3],s[3],cy[3]), fa4(cy[3],a[4],b[4],s[4],cy[4]), fa5(cy[4],a[5],b[5],s[5],cy[5]), fa6(cy[5],a[6],b[6],s[6],cy[6]), fa7(cy[6],a[7],b[7],s[7],cout);
endmodule
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