基本邏輯5 其他組合邏輯實驗
程式設計者可以練習七段顯示編碼器和ALU,乘法器等電路
程式設計者可以練習使用Table Statement
這格實驗可以練習使用Node
-- svnseg
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VHDL : svnseg.vhd |
Verilog : svnseg.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY svnseg IS PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); sc : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); sa : OUT STD_LOGIC ); END svnseg;
ARCHITECTURE a1 OF svnseg IS BEGIN
sa<='1';
PROCESS(d) BEGIN CASE d IS WHEN "0000" => sc<="1000000"; WHEN "0001" => sc<="1111001"; WHEN "0010" => sc<="0100100"; WHEN "0011" => sc<="0110000"; WHEN "0100" => sc<="0011001"; WHEN "0101" => sc<="0010010"; WHEN "0110" => sc<="0000010"; WHEN "0111" => sc<="1111000"; WHEN "1000" => sc<="0000000"; WHEN "1001" => sc<="0010000"; WHEN OTHERS => sc<="1111111"; END CASE; END PROCESS;
END a1;
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module svnseg ( d,sc,sa ); input[3:0] d; output[6:0] sc; output sa;
reg[6:0] sc;
assign sa=1'b1;
always @(d) begin case(d) 0 : sc=7'b1000000; 1 : sc=7'b1111001; 2 : sc=7'b0100100; 3 : sc=7'b0110000; 4 : sc=7'b0011001; 5 : sc=7'b0010010; 6 : sc=7'b0000010; 7 : sc=7'b1111000; 8 : sc=7'b0000000; 9 : sc=7'b0010000; default : sc=7'b1111111; endcase end
endmodule
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-- alu8
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VHDL : alu8.vhd |
Verilog : alu8.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY dlatch IS PORT ( a,b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END dlatch;
ARCHITECTURE a1 OF dlatch IS BEGIN
PROCESS(s,a,b) BEGIN CASE s IS WHEN "00" => y<=a+b; WHEN "01" => y<=a-b; WHEN "10" => y<=a AND b; WHEN "11" => y<=a OR b; WHEN OTHERS => y<="00000000"; END CASE; END PROCESS;
END PROCESS;
END a1;
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module alu8 ( s,a,b, y );
input[1:0] s; input[7:0] a,b; output[7:0] y;
reg[7:0] y;
always @(s or a or b) begin case(s) 2'b00 : y=a&b; 2'b01 : y=a|b; 2'b10 : y=a+b; 2'b11 : y=a-b; endcase end
endmodule
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-- cmult
Combinatorial Multiplier
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VHDL : cmult.vhd |
Verilog : cmult.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY cmult IS PORT ( a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END cmult;
ARCHITECTURE a1 OF cmult IS SIGNAL aa,ab,ac,ad : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ni : STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL nj : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN
aa<=a WHEN b(0)='1' ELSE "0000"; ab<=a WHEN b(1)='1' ELSE "0000"; ac<=a WHEN b(2)='1' ELSE "0000"; ad<=a WHEN b(3)='1' ELSE "0000";
ni<=aa+(ab&"0"); nj<=ni+(ac&"00"); y<=nj+(ad&"000");
END a1;
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module cmult ( a,b, y );
input[3:0] a,b; output[7:0] y;
wire[5:0] ni; wire[6:0] nj;
assign ni={2'b00,{4{b[0]}}&a}+{1'b0,{4{b[1]}}&a,1'b0}; assign nj={1'b0,ni}+{1'b0,{4{b[2]}}&a,2'b00}; assign y={1'b0,nj}+{1'b0,{4{b[3]}}&a,3'b000};
endmodule
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