基本邏輯6 記憶元件
程式設計者可以了解幾種基本記憶元件的結構及原理
這個實驗可以練習Post-Layout Simulation
-- dlatch
D type Latch或稱Transparent Latch, 因ge=1時, 輸入輸出如同transparent
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VHDL : dlatch.vhd |
Verilog : dlatch.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY dlatch IS PORT ( ge,dd : IN STD_LOGIC; qq : OUT STD_LOGIC ); END dlatch;
ARCHITECTURE a1 OF dlatch IS BEGIN PROCESS(ge,dd) BEGIN IF ge='1' THEN qq<=dd; END IF; END PROCESS;
END a1; |
module dlatch ( ge,dd, );
input ge,dd; output qq;
reg qq;
always @(ge or dd) if(ge) qq=dd;
endmodule
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-- flipflop
D type flip-flop, 由2個吃transparent串接組成
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VHDL : flipflop.vhd |
Verilog : flipflop.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY flipflop IS PORT ( mclk,dd : IN STD_LOGIC; qq : OUT STD_LOGIC ); END flipflop;
ARCHITECTURE a1 OF flipflop IS SIGNAL mm,ss : STD_LOGIC; BEGIN
PROCESS(mclk,dd) BEGIN IF mclk='0' THEN mm<=dd; END IF; END PROCESS;
PROCESS(mclk,mm) BEGIN IF mclk='1' THEN ss<=mm; END IF; END PROCESS;
qq<=ss;
END a1;
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module flipflop ( mclk,dd, );
input mclk,dd; output qq;
reg mm,ss;
always @(mclk or dd) if(~mclk) mm=dd;
always @(mclk or mm) if(mclk) ss=mm; assign qq=ss; endmodule
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