基本實驗7 State machine
這是一個簡單的State machine
程式設計者可以了解Mealy Output和Moore Output的特性
程式設計者可以練習實用的一個小State machine: oneshot產生器
-- tog
toggle
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VHDL : tog.vhd |
Verilog : tog.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY tog IS PORT ( mclk,en,ai : IN STD_LOGIC; pp,qq : OUT STD_LOGIC ); END tog;
ARCHITECTURE a1 OF tog IS SIGNAL ss : STD_LOGIC; BEGIN
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN IF ss='0' THEN qq<='0'; pp<='0'; IF en='1' THEN ss<='1'; ELSE ss<='0'; END IF; ELSE qq<='1'; pp<=ai; IF en='1' THEN ss<='0'; ELSE ss<='1'; END IF; END IF; END IF; END PROCESS;
END a1;
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module tog ( mclk,en,ai, pp,qq ); input mclk,en,ai; output pp,qq;
reg ss,pp,qq;
always @(posedge mclk) begin if(~ss) begin qq=1'b0; pp=1'b0; if(en) ss=1'b1; else ss=1'b0; end else begin qq=1'b1; pp=ai; if(en) ss=1'b0; else ss=1'b1; end end
endmodule
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-- oneshot
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VHDL : oneshot.vhd |
Verilog : oneshot.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY oneshot IS PORT ( mclk,di : IN STD_LOGIC; qq : OUT STD_LOGIC ); END oneshot;
ARCHITECTURE a1 OF oneshot IS SIGNAL ss : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN CASE ss IS WHEN "00" => IF di='1' THEN ss<="01"; END IF; WHEN "01" => ss<="10"; WHEN "10" => IF di='0' THEN ss<="00"; END IF; WHEN OTHERS => ss<="00"; END CASE; END IF; END PROCESS;
qq<=ss(0);
END a1;
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module oneshot ( mclk,di, );
input mclk,di; output qq;
reg[1:0] ss;
always @(posedge mclk) begin case(ss) 2'b00 : if(di) ss<=2'b01; 2'b01 : ss<=2'b10; 2'b10 : if(~di) ss<=2'b00; default : ss<=2'b00; endcase end
assign qq=ss[0];
endmodule
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