基本邏輯8 Sequence detector和Counter
程式設計者可以練習較複雜的State machine
了解Sequence detector的原理和動作
程式設計者可以練習Counter這種State machine分別以Case Statement或"+"Operator描述
-- seqdet
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VHDL : seqdet.vhd |
Verilog : seqdet.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY seqdet IS PORT ( mclk,di : IN STD_LOGIC; hit : OUT STD_LOGIC ); END seqdet;
ARCHITECTURE a1 OF seqdet IS SIGNAL ss,nss : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(mclk) BEGIN IF(mclk'EVENT AND mclk='1') THEN CASE(ss) IS WHEN "000" => IF(di='1') THEN ss<="001"; END IF; WHEN "001" => IF(di='0') THEN ss<="010"; END IF; WHEN "010" => IF(di='1') THEN ss<="011"; ELSE ss<="000"; END IF; WHEN "011" => IF(di='1') THEN ss<="100"; ELSE ss<="010"; END IF; WHEN "100" => IF(di='1') THEN ss<="001"; ELSE ss<="101"; END IF; WHEN "101" => IF(di='1') THEN ss<="011"; ELSE ss<="000"; END IF; WHEN OTHERS => ss<="000"; END CASE; END IF; END PROCESS;
hit<='1' WHEN (ss="101") ELSE '0';
END a1;
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module seqdet ( mclk,di, hit ); input mclk,di; output hit;
reg[2:0] ss,nss;
always @(posedge mclk) begin case(ss) 3'b000 : if(di) ss<=3'b001; 3'b001 : if(~di) ss<=3'b010; 3'b010 : begin if(di) ss<=3'b011; else ss<=3'b000; end 3'b011 : begin if(di) ss<=3'b100; else ss<=3'b010; end 3'b100 : begin if(di) ss<=3'b001; else ss<=3'b101; end 3'b101 : begin if(di) ss<=3'b011; else ss<=3'b000; end default : ss<=3'b000; endcase end
assign hit=(ss==3'b101);
endmodule
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-- cnt4
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VHDL : cnt4.vhd |
Verilog : cnt4.v |
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LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY cnt4 IS PORT ( mclk,en : IN STD_LOGIC; qq : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END cnt4;
ARCHITECTURE a1 OF cnt4 IS SIGNAL ss : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN CASE ss IS WHEN "0000" => IF en='1' THEN ss<="0001"; END IF; WHEN "0001" => IF en='1' THEN ss<="0010"; END IF; WHEN "0010" => IF en='1' THEN ss<="0011"; END IF; WHEN "0011" => IF en='1' THEN ss<="0100"; END IF; WHEN "0100" => IF en='1' THEN ss<="0101"; END IF; WHEN "0101" => IF en='1' THEN ss<="0110"; END IF; WHEN "0110" => IF en='1' THEN ss<="0111"; END IF; WHEN "0111" => IF en='1' THEN ss<="1000"; END IF; WHEN "1000" => IF en='1' THEN ss<="1001"; END IF; WHEN "1001" => IF en='1' THEN ss<="1010"; END IF; WHEN "1010" => IF en='1' THEN ss<="1011"; END IF; WHEN "1011" => IF en='1' THEN ss<="1100"; END IF; WHEN "1100" => IF en='1' THEN ss<="1101"; END IF; WHEN "1101" => IF en='1' THEN ss<="1110"; END IF; WHEN "1110" => IF en='1' THEN ss<="1111"; END IF; WHEN "1111" => IF en='1' THEN ss<="0000"; END IF; WHEN OTHERS => ss<="0000"; END CASE; END IF; END PROCESS;
qq<=ss; END a1;
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module cnt4 ( mclk,en, );
input mclk,en; output[3:0] qq;
reg[3:0] ss;
always @(posedge mclk) begin case(ss) 4'b0000 : if(en) ss=4'b0001; 4'b0001 : if(en) ss=4'b0010; 4'b0010 : if(en) ss=4'b0011; 4'b0011 : if(en) ss=4'b0100; 4'b0100 : if(en) ss=4'b0101; 4'b0101 : if(en) ss=4'b0110; 4'b0110 : if(en) ss=4'b0111; 4'b0111 : if(en) ss=4'b1000; 4'b1000 : if(en) ss=4'b1001; 4'b1001 : if(en) ss=4'b1010; 4'b1010 : if(en) ss=4'b1011; 4'b1011 : if(en) ss=4'b1100; 4'b1100 : if(en) ss=4'b1101; 4'b1101 : if(en) ss=4'b1110; 4'b1110 : if(en) ss=4'b1111; 4'b1111 : if(en) ss=4'b0000; endcase end
assign qq=ss;
endmodule
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