基本邏輯9 Accumulator (累加器) 和 Pipelined multiplier (管線化乘法器)
這些亦為廣義的State machine, 但一般所指的State machine極為電路中 "控制 "部分, "資料control 路徑 "部分, 則不稱State machine
程式設計者可以練習累加器和各種序向乘法器
了解Pipeline的原理和作法
-- accum
|
VHDL : accum.vhd |
Verilog : accum.v |
|
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY accum IS PORT ( mclk,en : IN STD_LOGIC; di : IN STD_LOGIC_VECTOR(7 DOWNTO 0); acco : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END accum;
ARCHITECTURE a1 OF accum IS SIGNAL acc : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN IF en='1' THEN acc<=acc+di; END IF; END IF; END PROCESS;
acco<=acc;
END a1;
|
module accum ( mclk,en,di, acco );
input mclk,en; input[7:0] di; output[15:0] acco;
reg[15:0] acco;
always @(posedge mclk) begin if(en) acco<=acco+{8'h00,di}; end
endmodule
|
|
VHDL : taccum.vhd |
Verilog : taccum.v |
|
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY taccum IS PORT ( mclk : IN STD_LOGIC; acco : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END taccum;
ARCHITECTURE a1 OF taccum IS SIGNAL cnt : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL vdd : STD_LOGIC; COMPONENT accum PORT ( mclk,en : IN STD_LOGIC; di : IN STD_LOGIC_VECTOR(7 DOWNTO 0); acco : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT;
BEGIN
vdd<='1';
au1 : accum PORT MAP(mclk=>mclk,en=>vdd,di=>cnt,acco=>acco);
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN cnt<=cnt+1; END IF; END PROCESS; END a1;
|
module taccum ( mclk, acco );
input mclk; output[15:0] acco;
reg[7:0] cnt;
accum acc(mclk,1'b1,cnt,acco);
always @(posedge mclk) cnt<=cnt+1;
endmodule
|
-- npmult
|
VHDL : npmult.vhd |
Verilog : npmult.v |
|
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
ENTITY npmult IS PORT ( mclk : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END npmult;
ARCHITECTURE a1 OF npmult IS SIGNAL aa,ab,ac,ad,as,bs : STD_LOGIC_VECTOR(3 DOWNTO 0); --SIGNAL ni : STD_LOGIC_VECTOR(5 DOWNTO 0); --SIGNAL nj : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN
PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN as<=a; bs<=b; END IF; END PROCESS;
aa<=as WHEN bs(0)='1' ELSE "0000"; ab<=as WHEN bs(1)='1' ELSE "0000"; ac<=as WHEN bs(2)='1' ELSE "0000"; ad<=as WHEN bs(3)='1' ELSE "0000"; --ni<=aa+(ab&"0"); --nj<=ni+(ac&"00"); -- --PROCESS(mclk) --BEGIN --IF mclk'EVENT AND mclk='1' THEN -- y<=nj+(ad&"000"); --END IF; --END PROCESS; PROCESS(mclk) BEGIN IF mclk'EVENT AND mclk='1' THEN y<=aa+(ab&"0")+(ac&"00")+(ad&"000"); END IF END PROCESS;
END a1;
|
module npmult ( mclk,a,b, y );
input mclk; input[3:0] a,b; output[7:0] y;
reg[3:0] as,bs; reg[7:0] y;
//wire[5:0] ni; //wire[6:0] nj;
always @(posedge mclk) begin as<=a; bs<=b; end
//assign ni={2'b00,{4{bs[0]}}&as}+{1'b0,{4{bs[1]}}&as,1'b0}; //assign nj={1'b0,ni}+{1'b0,{4{bs[2]}}&as,2'b00}; // //always @(posedge mclk) //y<={1'b0,nj}+{1'b0,{4{bs[3]}}&as,3'b000};
//always @(posedge mclk) //y<={1'b0,{1'b0,{2'b00,{4{bs[0]}}&as}+{1'b0,{4{bs[1]}}&as,1'b0}} // +{1'b0,{4{bs[2]}}&as,2'b00}}+{1'b0,{4{bs[3]}}&as,3'b000};
always @(posedge mclk) y<={4'b0000,{4{bs[0]}}&as}+{3'b000,{4{bs[1]}}&as,1'b0}+ {2'b00,{4{bs[2]}}&as,2'b00}+{1'b0,{4{bs[3]}}&as,3'b000};
endmodule
|
-- pmult
|
VHDL : pmult.vhd |
Verilog : pmult.v |
