FPGA 實驗 <
ISE + IDS >
Lab1 : Leds
▋ Design Codes
leds.c
`timescale 1ns / 1ps
module leds
(
mclk,
ledo,
dpswi
);
input mclk;
output [23:0] ledo;
input [7:0] dpswi;
reg[23:0] dcnt;
assign ledo={dcnt[23:16],dcnt[23:16],dpswi};
always @(posedge mclk)
begin
dcnt<=dcnt+1;
end
endmodule
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