FPGA 實驗 <
ISE + IDS >
Lab3 : Timer
▋ Design Codes
timer.v
module timer
(
mclk,btna,btnb,
sc,sa
);
input mclk,btna,btnb;
output[7:0] sc;
output[3:0] sa;
reg[24:0] divcnt;
reg[7:0] sc;
reg[3:0] sa,cnta,cntc,cntout,stmode,nstmode;
reg[2:0] cntb,cntd;
reg[1:0] stdb,stka,stkb;
reg btnas,btnbs,dota,dotb,dotc,dotd;
wire[1:0] sel;
wire divcov,pulsea;
always @(posedge mclk)
begin
if(divcov)
divcnt<=0;
else divcnt<=divcnt+1;
end
assign divcov=(divcnt==799999);
assign pulsea=divcov&(stmode==4'b0000);
always @(posedge mclk)
begin
if(pulsea | stkb[0]&stmode[3])
begin
if(cnta==9) cnta<=0;
else cnta<=cnta+1;
end
end
always @(posedge mclk)
begin
if(pulsea&(cnta==9) | stkb[0]&stmode[2])
begin
if(cntb==5) cntb<=0;
else cntb<=cntb+1;
end
end
always @(posedge mclk)
begin
if(pulsea&(cnta==9)&(cntb==5) | stkb[0]&stmode[1])
begin
if(cntc==9) cntc<=0;
else cntc<=cntc+1;
end
end
always @(posedge mclk)
begin
if(pulsea&(cnta==9)&(cntb==5)&(cntc==9) | stkb[0]&stmode[0])
begin
if(cntd==5) cntd<=0;
else cntd<=cntd+1;
end
end
assign sel=divcnt[9:8];
always @(sel or cnta or cntb or cntc or cntd or dota
or dotb or dotc or dotd)
begin
case(sel)
0 : begin cntout={1'b0,cntd}; sa=4'b1000; sc[7]=dotd; end
1 : begin cntout=cntc; sa=4'b0100; sc[7]=dotc; end
2 : begin cntout={1'b0,cntb}; sa=4'b0010; sc[7]=dotb; end
3 : begin cntout=cnta; sa=4'b0001; sc[7]=dota; end
endcase
case(cntout)
0 : sc[6:0]=7'b0111111;
1 : sc[6:0]=7'b0000110;
2 : sc[6:0]=7'b1011011;
3 : sc[6:0]=7'b1001111;
4 : sc[6:0]=7'b1100110;
5 : sc[6:0]=7'b1101101;
6 : sc[6:0]=7'b1111101;
7 : sc[6:0]=7'b0000111;
8 : sc[6:0]=7'b1111111;
9 : sc[6:0]=7'b1101111;
default : sc[6:0]=7'b0000000;
endcase
end
always @(posedge mclk)
begin
case(stdb)
2'b00 : if(divcnt[15]) stdb<=2'b01;
2'b01 : stdb<=2'b10;
2'b10 : if(~divcnt[15]) stdb<=2'b00;
2'b11 : stdb<=00;
endcase
end
always @(posedge mclk)
begin
btnas<=btna;
btnbs<=btnb;
end
always @(posedge mclk)
begin
case(stka)
2'b00 : if(btnas&stdb[0]) stka<=2'b01;
2'b01 : stka<=2'b10;
2'b10 : if(~btnas&stdb[0]) stka<=2'b00;
2'b11 : stka<=2'b00;
endcase
end
always @(posedge mclk)
begin
case(stkb)
2'b00 : if(btnbs&stdb[0]) stkb<=2'b01;
2'b01 : stkb<=2'b10;
2'b10 : if(~btnbs&stdb[0]) stkb<=2'b00;
2'b11 : stkb<=2'b00;
endcase
end
always @(posedge mclk)
stmode<=nstmode;
always @(stmode or divcnt or stka)
begin
nstmode=stmode;
casex(stmode)
4'b0000 : begin
{dotd,dotc,dotb,dota}={~divcnt[19],divcnt[19],divcnt[19],~divcnt[19]};
if(stka[0]) nstmode=4'b0001;
end
4'bxxx1 : begin
{dotd,dotc,dotb,dota}={divcnt[19],3'b000};
if(stka[0]) nstmode=4'b0010;
end
4'bxx1x : begin
{dotd,dotc,dotb,dota}={1'b0,divcnt[19],2'b00};
if(stka[0]) nstmode=4'b0100;
end
4'bx1xx : begin
{dotd,dotc,dotb,dota}={2'b00,divcnt[19],1'b0};
if(stka[0]) nstmode=4'b1000;
end
4'b1xxx : begin
{dotd,dotc,dotb,dota}={3'b000,divcnt[19]};
if(stka[0]) nstmode=4'b0000;
end
default : begin {dotd,dotc,dotb,dota}=4'b0; end
endcase
end
endmodule
